/* Copyright (c) 2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ &soc { sde_kms: qcom,sde_kms@900000 { compatible = "qcom,sde-kms"; reg = <0x00900000 0x90000>, <0x009b0000 0x1040>, <0x009b8000 0x1040>; reg-names = "mdp_phys", "vbif_phys", "vbif_nrt_phys"; clocks = <&clock_mmss clk_mdss_ahb_clk>, <&clock_mmss clk_mdss_axi_clk>, <&clock_mmss clk_mdp_clk_src>, <&clock_mmss clk_mdss_mdp_vote_clk>, <&clock_mmss clk_smmu_mdp_axi_clk>, <&clock_mmss clk_smmu_mdp_ahb_clk>, <&clock_mmss clk_smmu_rot_axi_clk>, <&clock_mmss clk_smmu_rot_ahb_clk>, <&clock_mmss clk_mmagic_mdss_axi_clk>, <&clock_mmss clk_mdss_vsync_clk>; clock-names = "iface_clk", "bus_clk", "core_clk_src", "core_clk", "iommu_mdp_axi_clk", "iommu_mdp_ahb_clk", "iommu_rot_axi_clk", "iommu_rot_ahb_clk", "mmagic_clk", "vsync_clk"; mmagic-supply = <&gdsc_mmagic_mdss>; vdd-supply = <&gdsc_mdss>; interrupt-parent = <&intc>; interrupts = <0 83 0>; interrupt-controller; #interrupt-cells = <1>; iommus = <&mdp_smmu 0>; smmu_kms_unsec: qcom,smmu_kms_unsec_cb { compatible = "qcom,smmu_kms_unsec"; iommus = <&mdp_smmu 0>; }; smmu_nrt_unsec: qcom,smmu_nrt_unsec_cb { compatible = "qcom,smmu_nrt_unsec"; iommus = <&rot_smmu 0>; }; smmu_kms_sec: qcom,smmu_kms_sec_cb { compatible = "qcom,smmu_kms_sec"; iommus = <&mdp_smmu 1>; }; smmu_nrt_sec: qcom,smmu_nrt_sec_cb { compatible = "qcom,smmu_nrt_sec"; iommus = <&rot_smmu 1>; }; }; sde_dsi0: qcom,sde_dsi_ctrl0@994000 { compatible = "qcom,dsi-ctrl-hw-v1.4"; label = "dsi-ctrl-0"; cell-index = <0>; reg = <0x994000 0x400>, <0x828000 0x108>; reg-names = "dsi_ctrl", "mmss_misc"; gdsc-supply = <&gdsc_mdss>; vdda-supply = <&pm8994_l2>; vcca-supply = <&pm8994_l28>; clocks = <&clock_mmss clk_mdss_mdp_vote_clk>, <&clock_mmss clk_mdss_ahb_clk>, <&clock_mmss clk_mmss_misc_ahb_clk>, <&clock_mmss clk_mdss_axi_clk>, <&clock_mmss clk_mdss_byte0_clk>, <&clock_mmss clk_mdss_pclk0_clk>, <&clock_mmss clk_mdss_esc0_clk>, <&clock_mmss clk_byte0_clk_src>, <&clock_mmss clk_pclk0_clk_src>; clock-names = "mdp_core_clk", "iface_clk", "core_mmss_clk", "bus_clk", "byte_clk", "pixel_clk", "core_clk", "byte_clk_rcg", "pixel_clk_rcg"; /* axi bus scale settings */ qcom,msm-bus,name = "mdss_dsi0"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <22 512 0 0>, <22 512 0 1000>; interrupt-parent = <&sde_kms>; interrupts = <4 0>; qcom,core-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,core-supply-entry@0 { reg = <0>; qcom,supply-name = "gdsc"; qcom,supply-min-voltage = <0>; qcom,supply-max-voltage = <0>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; }; qcom,ctrl-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,ctrl-supply-entry@0 { reg = <0>; qcom,supply-name = "vcca"; qcom,supply-min-voltage = <925000>; qcom,supply-max-voltage = <925000>; qcom,supply-enable-load = <17000>; qcom,supply-disable-load = <32>; }; qcom,ctrl-supply-entry@1 { reg = <0>; qcom,supply-name = "vdda"; qcom,supply-min-voltage = <1250000>; qcom,supply-max-voltage = <1250000>; qcom,supply-enable-load = <18160>; qcom,supply-disable-load = <1>; }; }; }; sde_dsi1: qcom,sde_dsi_ctrl1@996000 { compatible = "qcom,dsi-ctrl-hw-v1.4"; label = "dsi-ctrl-1"; cell-index = <1>; reg = <0x996000 0x400>, <0x828000 0x108>; reg-names = "dsi_ctrl", "mmss_misc"; gdsc-supply = <&gdsc_mdss>; vdda-supply = <&pm8994_l2>; vcca-supply = <&pm8994_l28>; clocks = <&clock_mmss clk_mdss_mdp_vote_clk>, <&clock_mmss clk_mdss_ahb_clk>, <&clock_mmss clk_mmss_misc_ahb_clk>, <&clock_mmss clk_mdss_axi_clk>, <&clock_mmss clk_mdss_byte1_clk>, <&clock_mmss clk_mdss_pclk1_clk>, <&clock_mmss clk_mdss_esc1_clk>, <&clock_mmss clk_byte1_clk_src>, <&clock_mmss clk_pclk1_clk_src>; clock-names = "mdp_core_clk", "iface_clk", "core_mmss_clk", "bus_clk", "byte_clk", "pixel_clk", "core_clk", "byte_clk_rcg", "pixel_clk_rcg"; /* axi bus scale settings */ qcom,msm-bus,name = "mdss_dsi1"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <22 512 0 0>, <22 512 0 1000>; interrupt-parent = <&sde_kms>; interrupts = <5 0>; qcom,core-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,core-supply-entry@0 { reg = <0>; qcom,supply-name = "gdsc"; qcom,supply-min-voltage = <0>; qcom,supply-max-voltage = <0>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; }; qcom,ctrl-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,ctrl-supply-entry@0 { reg = <0>; qcom,supply-name = "vdda"; qcom,supply-min-voltage = <1250000>; qcom,supply-max-voltage = <1250000>; qcom,supply-enable-load = <18160>; qcom,supply-disable-load = <1>; }; qcom,ctrl-supply-entry@1 { reg = <0>; qcom,supply-name = "vcca"; qcom,supply-min-voltage = <925000>; qcom,supply-max-voltage = <925000>; qcom,supply-enable-load = <18050>; qcom,supply-disable-load = <32>; }; }; }; sde_dsi_phy0: qcom,sde_dsi_phy0@994400 { compatible = "qcom,dsi-phy-v4.0"; label = "dsi-phy-0"; cell-index = <0>; reg = <0x994400 0x588>; reg-names = "dsi_phy"; gdsc-supply = <&gdsc_mdss>; vdda-supply = <&pm8994_l2>; clocks = <&clock_mmss clk_mdss_mdp_vote_clk>, <&clock_mmss clk_mdss_ahb_clk>, <&clock_mmss clk_mmss_misc_ahb_clk>, <&clock_mmss clk_mdss_axi_clk>; clock-names = "mdp_core_clk", "iface_clk", "core_mmss_clk", "bus_clk"; qcom,platform-strength-ctrl = [ff 06 ff 06 ff 06 ff 06 ff 00]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; qcom,platform-lane-config = [00 00 10 0f 00 00 10 0f 00 00 10 0f 00 00 10 0f 00 00 10 8f]; qcom,core-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,core-supply-entry@0 { reg = <0>; qcom,supply-name = "gdsc"; qcom,supply-min-voltage = <0>; qcom,supply-max-voltage = <0>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; }; qcom,phy-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,phy-supply-entry@0 { reg = <0>; qcom,supply-name = "vdda"; qcom,supply-min-voltage = <1250000>; qcom,supply-max-voltage = <1250000>; qcom,supply-enable-load = <2500>; qcom,supply-disable-load = <1>; }; }; }; sde_dsi_phy1: qcom,sde_dsi_phy1@996400 { compatible = "qcom,dsi-phy-v4.0"; label = "dsi-phy-1"; cell-index = <1>; reg = <0x996400 0x588>; reg-names = "dsi_phy"; gdsc-supply = <&gdsc_mdss>; vdda-supply = <&pm8994_l2>; clocks = <&clock_mmss clk_mdss_mdp_vote_clk>, <&clock_mmss clk_mdss_ahb_clk>, <&clock_mmss clk_mmss_misc_ahb_clk>, <&clock_mmss clk_mdss_axi_clk>; clock-names = "mdp_core_clk", "iface_clk", "core_mmss_clk", "bus_clk"; qcom,platform-strength-ctrl = [ff 06 ff 06 ff 06 ff 06 ff 00]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; qcom,platform-lane-config = [00 00 10 0f 00 00 10 0f 00 00 10 0f 00 00 10 0f 00 00 10 8f]; qcom,core-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,core-supply-entry@0 { reg = <0>; qcom,supply-name = "gdsc"; qcom,supply-min-voltage = <0>; qcom,supply-max-voltage = <0>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; }; qcom,phy-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,phy-supply-entry@0 { reg = <0>; qcom,supply-name = "vdda"; qcom,supply-min-voltage = <1250000>; qcom,supply-max-voltage = <1250000>; qcom,supply-enable-load = <2500>; qcom,supply-disable-load = <1>; }; }; }; sde_hdmi: qcom,sde_hdmi@9a0000 { compatible = "qcom,hdmi-tx-8996"; reg = <0x009a0000 0x50c>, <0x00070000 0x6158>, <0x009e0000 0xfff>; reg-names = "core_physical", "qfprom_physical", "hdcp_physical"; clocks = <&clock_mmss clk_mdss_mdp_vote_clk>, <&clock_mmss clk_mdss_ahb_clk>, <&clock_mmss clk_mdss_hdmi_clk>, <&clock_mmss clk_mdss_hdmi_ahb_clk>, <&clock_mmss clk_mdss_extpclk_clk>; clock-names = "mdp_core_clk", "iface_clk", "core_clk", "alt_iface_clk", "extp_clk"; interrupt-parent = <&sde_kms>; interrupts = <8 0>; hpd-gdsc-supply = <&gdsc_mdss>; qcom,hdmi-tx-ddc-clk-gpio = <&tlmm 32 0>; qcom,hdmi-tx-ddc-data-gpio = <&tlmm 33 0>; qcom,hdmi-tx-hpd-gpio = <&tlmm 34 0>; qcom,hdmi-tx-mux-en-gpio = <&tlmm 27 0>; qcom,hdmi-tx-mux-sel-gpio = <&tlmm 83 0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&mdss_hdmi_hpd_active &mdss_hdmi_ddc_active &mdss_hdmi_cec_active>; pinctrl-1 = <&mdss_hdmi_hpd_suspend &mdss_hdmi_ddc_suspend &mdss_hdmi_cec_suspend>; sde_hdmi_audio: qcom,sde-hdmi-audio-rx { compatible = "qcom,msm-hdmi-audio-codec-rx"; }; }; };