/*
 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/ {
	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU4>;
				};
				core1 {
					cpu = <&CPU5>;
				};
				core2 {
					cpu = <&CPU6>;
				};
				core3 {
					cpu = <&CPU7>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU0>;
				};
				core1 {
					cpu = <&CPU1>;
				};
				core2 {
					cpu = <&CPU2>;
				};
				core3 {
					cpu = <&CPU3>;
				};
			};
		};

		CPU0: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x100>;
			enable-method = "psci";
			qcom,acc = <&acc0>;
			qcom,limits-info = <&mitigation_profile0>;
			next-level-cache = <&L2_1>;
			L2_1: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      power-domain = <&l2ccc_1>;
			      /* A53 L2 dump not supported */
			      qcom,dump-size = <0x0>;
			};
			L1_I_100: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};
			L1_D_100: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};
		};

		CPU1: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x101>;
			enable-method = "psci";
			qcom,acc = <&acc1>;
			qcom,limits-info = <&mitigation_profile1>;
			next-level-cache = <&L2_1>;
			L1_I_101: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};
			L1_D_101: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};
		};

		CPU2: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x102>;
			enable-method = "psci";
			qcom,acc = <&acc2>;
			qcom,limits-info = <&mitigation_profile2>;
			next-level-cache = <&L2_1>;
			L1_I_102: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};
			L1_D_102: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};
		};

		CPU3: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x103>;
			enable-method = "psci";
			qcom,acc = <&acc3>;
			qcom,limits-info = <&mitigation_profile3>;
			next-level-cache = <&L2_1>;
			L1_I_103: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};
			L1_D_103: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};
		};

		CPU4: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "psci";
			qcom,acc = <&acc4>;
			qcom,limits-info = <&mitigation_profile4>;
			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      power-domain = <&l2ccc_0>;
			      qcom,dump-size = <0x0>;
			};
			L1_I_0: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};
			L1_D_0: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};
		};

		CPU5: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			enable-method = "psci";
			qcom,acc = <&acc5>;
			qcom,limits-info = <&mitigation_profile4>;
			next-level-cache = <&L2_0>;
			L1_I_1: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};
			L1_D_1: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};
		};

		CPU6: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			enable-method = "psci";
			qcom,acc = <&acc6>;
			qcom,limits-info = <&mitigation_profile4>;
			next-level-cache = <&L2_0>;
			L1_I_2: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};
			L1_D_2: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};
		};

		CPU7: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			enable-method = "psci";
			qcom,acc = <&acc7>;
			qcom,limits-info = <&mitigation_profile4>;
			next-level-cache = <&L2_0>;
			L1_I_3: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};
			L1_D_3: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};
		};
	};
};

&soc {
	l2ccc_0: clock-controller@b111000 {
		compatible = "qcom,8937-l2ccc";
		reg = <0x0b111000 0x1000>;
	};

	l2ccc_1: clock-controller@b011000 {
		compatible = "qcom,8937-l2ccc";
		reg = <0x0b011000 0x1000>;
	};

	acc0:clock-controller@b088000 {
		compatible = "qcom,arm-cortex-acc";
		reg = <0x0b088000 0x1000>;
	};

	acc1:clock-controller@b098000 {
		compatible = "qcom,arm-cortex-acc";
		reg = <0x0b098000 0x1000>;
	};

	acc2:clock-controller@b0a8000 {
		compatible = "qcom,arm-cortex-acc";
		reg = <0x0b0a8000 0x1000>;
	};

	acc3:clock-controller@b0b8000 {
		compatible = "qcom,arm-cortex-acc";
		reg = <0x0b0b8000 0x1000>;
	};

	acc4:clock-controller@b188000 {
		compatible = "qcom,arm-cortex-acc";
		reg = <0x0b188000 0x1000>;
	};

	acc5:clock-controller@b198000 {
		compatible = "qcom,arm-cortex-acc";
		reg = <0x0b198000 0x1000>;
	};

	acc6:clock-controller@b1a8000 {
		compatible = "qcom,arm-cortex-acc";
		reg = <0x0b1a8000 0x1000>;
	};

	acc7:clock-controller@b1b8000 {
		compatible = "qcom,arm-cortex-acc";
		reg = <0x0b1b8000 0x1000>;
	};

	cpuss_dump {
		compatible = "qcom,cpuss-dump";
		qcom,l2_dump0 {
			/* L2 cache dump for A53 cluster */
			qcom,dump-node = <&L2_0>;
			qcom,dump-id = <0xC0>;
		};
		qcom,l2_dump1 {
			/* L2 cache dump for A53 cluster */
			qcom,dump-node = <&L2_1>;
			qcom,dump-id = <0xC1>;
		};
		qcom,l1_i_cache0 {
			qcom,dump-node = <&L1_I_0>;
			qcom,dump-id = <0x60>;
		};
		qcom,l1_i_cache1 {
			qcom,dump-node = <&L1_I_1>;
			qcom,dump-id = <0x61>;
		};
		qcom,l1_i_cache2 {
			qcom,dump-node = <&L1_I_2>;
			qcom,dump-id = <0x62>;
		};
		qcom,l1_i_cache3 {
			qcom,dump-node = <&L1_I_3>;
			qcom,dump-id = <0x63>;
		};
		qcom,l1_i_cache100 {
			qcom,dump-node = <&L1_I_100>;
			qcom,dump-id = <0x64>;
		};
		qcom,l1_i_cache101 {
			qcom,dump-node = <&L1_I_101>;
			qcom,dump-id = <0x65>;
		};
		qcom,l1_i_cache102 {
			qcom,dump-node = <&L1_I_102>;
			qcom,dump-id = <0x66>;
		};
		qcom,l1_i_cache103 {
			qcom,dump-node = <&L1_I_103>;
			qcom,dump-id = <0x67>;
		};
		qcom,l1_d_cache0 {
			qcom,dump-node = <&L1_D_0>;
			qcom,dump-id = <0x80>;
		};
		qcom,l1_d_cache1 {
			qcom,dump-node = <&L1_D_1>;
			qcom,dump-id = <0x81>;
		};
		qcom,l1_d_cache2 {
			qcom,dump-node = <&L1_D_2>;
			qcom,dump-id = <0x82>;
		};
		qcom,l1_d_cache3 {
			qcom,dump-node = <&L1_D_3>;
			qcom,dump-id = <0x83>;
		};
		qcom,l1_d_cache100 {
			qcom,dump-node = <&L1_D_100>;
			qcom,dump-id = <0x84>;
		};
		qcom,l1_d_cache101 {
			qcom,dump-node = <&L1_D_101>;
			qcom,dump-id = <0x85>;
		};
		qcom,l1_d_cache102 {
			qcom,dump-node = <&L1_D_102>;
			qcom,dump-id = <0x86>;
		};
		qcom,l1_d_cache103 {
			qcom,dump-node = <&L1_D_103>;
			qcom,dump-id = <0x87>;
		};
	};
};